MATCHING OF CELLS – THE SUBSYSTEM OF THE AUTOMATION HIERARCHICAL PROCESS TOLERANT DESIGN OF CMOS VLSI MACROBLOCKS LAYOUT

The results of researches in the field of automation hierarchical process tolerant design of CMOS VLSI macroblocks are presented.Describes the developed software tools for the design topology of the macroblocks and the methodology hierarchical topology design using the graphical editor of the subsystem “Matching of Cells” are described.

Authors: S. E. Mironov, A. Yu. Vasilev

Direction: Informatics and Computer Technologies

Keywords: Hierarchical layout design, layout compaction, process tolerant design, design automation

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