METHODIC OF STRUCTURAL AND TOPOLOGICAL OPTIMIZATION REGULAR VLSI MACRO-BLOCKS

The questions of structural optimization of VLSI regular macro-blocks layout are considered in examples the pipelined multiplier.Methodic of structure and topological optimization for regular VLSI macro-blocks to reduce area of SoC is suggested, using the analysis results processes of reorganizations of layout plans VLSI macro-blocks.

Authors: S. E. Mironov, N. M. Safyannikov, A. K. Frolkin

Direction: Informatics, management and Computer Technology

Keywords: Regular VLSI macro-blocks, structural and topological optimization, pipelined multiplier

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