COMPUTER-AIDED DESIGN FACILITIES USING PARAMETERIZED CELLS FOR HIERARCHIC MACROBLOCKS VLSI
The article is devoted to the description of the shortcomings of parameterized multiaxis VLSI cells layout compaction algorithm. It provides a method for removing them developed for computer-aided design facilities of hierarchic macroblocks VLSI. Software tools for generating the specification of cells, verification and correction specifications and layout are described.
Authors: S. E. Mironov, A. А. Baranov, T. O. Efimova
Direction: Informatics, management and Computer Technology
Keywords: Process-tolerant layout design, algorithm of VLSI cells layout compaction, multiaxis method for layout design, verification and correction specifications and layouts of cells, parameterized layouts of cells
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