COMPENSATION OF ABSENCE OF LAYOUT CORRECTION PHASE IN COMPACTION ALGORITHM

The article is devoted to the description of the shortcomings of VLSI cells layout compaction algorithm in one pass (without correction of results). Describes how to offset the absence of correction phase in algorithm of layout compaction.

Authors: A. V. Bessonov, K. A. Knop, Y. T. Lyachek

Direction: Informatics, management and Computer Technology

Keywords: Process-tolerant layout design, algorithm of VLSI cells layout compaction

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