Algorithm for close-packed placement of transistors, taking into account the features of the topological implementation of VLSI cells

A combinatorial algorithm for placing cell components proposed for automate the process of designing the topology of integrated circuits. When creating a cell topology, the algorithm allows you to use pre-designed topology fragments, which simplifies and speeds up the process of placing components. To reduce the area of cells, various techniques were use related to the characteristics of the objects being implemented (LSI cells). Reducing the topology area occupied by transistors and switching components achieved by proximate connecting the drain-source regions of the transistors and directly connecting the gates of the transistors. Reducing the area of free zones ensured by mirror alternation of pairs of lines of transistors of different conductivity types, which reduces the number of zones separating them, in which contacts to the substrate and pocket must be located to combat parasitic currents. To speed up the comparative analysis of intermediate results of component placement, an indirect assessment of the quality of routing options provided.

Authors: P. M. Shiryaev, S. E. Mironov

Direction: Informatics, Computer Technologies And Control

Keywords: placement algorithm; placement and routing; density integrated circuit layout design; technological invariance

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