CLOSE-PACKED DESIGN OF CMOS LSI CELLS LAYOUT BASED ON GRAPH AND COMBINATORIAL METHODS

Is devoted to the research results description in the field of creating of software generation tools for close-packed layout of CMOS LSI cells in a process tolerant concept. The developed software tools generate a textual description of process tolerant sketches of the cell layout on a virtual coordinate grid. At the request of the consumer (the developer of integrated circuits large fragments), the process tolerant cell layout description can be quickly adapted to the required design rules of the manufacturer using one-dimensional layout compaction algorithms. Moreover, in the process of adaptation, in addition to design rules, additional restrictions on the dimensions and pins coordinates can take into account, which allows you to configure the cell layout not only for design rules, but also for the cell library requirements. High packing density of cells provided by graph and combinatorial transistors placement methods. The developed software for cell layout generation allows the user to set the required for pins coordinates and layout layers in which they will held.

Authors: K. M. Zibarev, S. E. Mironov, A. K. Frolkin

Direction: Informatics, Computer Technologies And Control

Keywords: Cells layout, LSI, layout optimization, transistor placement, link tracing, layout compaction

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