LSI CAD SYSTEM TOPDESIGN OF VIRTUAL SYMBOLIC DESIGNING OF PARAMETERIZED CMOS FRAGMENTS

Computer-aided design (CAD) TopDesign of fragments of large-scale integrated circuits (LSI) is consider. CAD TopDesign includes an integrated graphical environment TopDesgn for layout designing of CMOS LSI fragments with parameterization at the levels of layout and technology, including SCMOS [7] up to 0.18 microns. The second component of the CAD system is a subsystem of automation of specialized silicon compilers (SSC) fragments designing. This means automation of designing of SSC programs, where the input is the fragment parameters at all levels – informational, algorithmic, structural, circuitry, layout, technological, – and output – layout in a given CMOS technology from fairly broad generic class. Development was one of the winners of the competition-2002 of the Company INTEL on the former Soviet Union space. CAD TopDesign can be supply to practical use.

Authors: I. S. Zuev

Direction: Informatics and Computer Technologies

Keywords: LSI fragment, CAD, complementary MOS (CMOS) technology, parameterization of fragment at all levels, spe-cialized silicon compiler (SSC), technology invariant SSC project, symbolic level layout designing, multinode model of layout element, poly-coordinate layout model of designing

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